Optimizing Double Data Rate 3 (DDR3) Memory Settings in New 11th-Generation PowerEdge Servers
Date
:
6/1/2009
New 11th-generation PowerEdge™ R610 and PowerEdge R710 rack servers, PowerEdge T610 tower servers, and PowerEdge M610 and PowerEdge M710 blade servers take advantage of the Intel® Xeon® processor 5500 series, which utilizes Double Data Rate 3 (DDR3) memory. By providing the flexibility to configure up to three memory channels per processor and choose from high-performance, balanced-performance, high-capacity and mirror modes, the DDR3 architecture enables administrators to optimize memory configurations to suit specific requirements for a wide range of enterprise-usage scenarios.
Each processor in the 11th-generation PowerEdge servers includes three separate memory controller hubs (MCHs) within the processor pack, helping to avoid the requirement to transfer memory transactions between the processor and an external device. This design, however, introduces considerations about the appropriate way to populate and configure a system based on specific requirements for reliability, availability and serviceability (RAS) features, and speed. These servers also support both error-correcting code (ECC) DDR3 registered dual in-line memory modules (RDIMMs) and ECC DDR3 unbuffered DIMMs (UDIMMs). The memory interface supports memory demand and patrol scrubbing, single-bit error correction, and multi-bit error corrections. RDIMMs are suitable for a large amount of memory, extensive RAS features and maximum expandability, and offer address parity. However, unless business requirements call for very high memory capacity, UDIMM ECC is typically a cost-effective alternative to a comparable RDIMM configuration. Memory optimized, advanced ECC and mirror modes, meanwhile, offer the flexibility to match specific applications or purposes, enhancing long-term cost-effectiveness.
DDR3 is designed to support a range of performance requirements for enterprise applications and virtualized environments. Following best-practices guidelines for various usage scenarios helps administrators configure DDR3 memory options for optimal performance, capacity, data integrity and energy efficiency.
Each processor in the 11th-generation PowerEdge servers includes three separate memory controller hubs (MCHs) within the processor pack, helping to avoid the requirement to transfer memory transactions between the processor and an external device. This design, however, introduces considerations about the appropriate way to populate and configure a system based on specific requirements for reliability, availability and serviceability (RAS) features, and speed. These servers also support both error-correcting code (ECC) DDR3 registered dual in-line memory modules (RDIMMs) and ECC DDR3 unbuffered DIMMs (UDIMMs). The memory interface supports memory demand and patrol scrubbing, single-bit error correction, and multi-bit error corrections. RDIMMs are suitable for a large amount of memory, extensive RAS features and maximum expandability, and offer address parity. However, unless business requirements call for very high memory capacity, UDIMM ECC is typically a cost-effective alternative to a comparable RDIMM configuration. Memory optimized, advanced ECC and mirror modes, meanwhile, offer the flexibility to match specific applications or purposes, enhancing long-term cost-effectiveness.
DDR3 is designed to support a range of performance requirements for enterprise applications and virtualized environments. Following best-practices guidelines for various usage scenarios helps administrators configure DDR3 memory options for optimal performance, capacity, data integrity and energy efficiency.
